1. Technical Field
The present invention relates generally to a test mode signal generation circuit, and more particularly, to a test mode signal generation circuit which generates test mode signals from address signals.
2. Related Art
A semiconductor memory apparatus has various test modes for checking fails that occur during processes. Recent results show that as processes for fabricating a semiconductor memory apparatus are refined, fails increasingly occur, and the number of test modes necessary to check the fails that increasingly occur increases.
In a conventional test mode signal generation method, a plurality of test mode signals (TM<0:M>) are generated by decoding a plurality of address signals (A<0:N>). For example, if 7 addresses are inputted to generate test mode signals, test mode signals capable of entering 128 different test modes may be generated. Accordingly, in the case where the test mode signals are directly transmitted through global lines, the number of the global lines must be 128. The more global lines that are disposed in a peripheral region where a large number of circuits are provided for normal operations of a semiconductor apparatus, wiring increases in complexity and a layout margin decreases. Also, in the conventional test mode signal generation method, a limited number of test mode signals must be generated since the number of address signals is limited.